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High Frequency Divider/PLL Synthesizer ADF4007
FEATURES
7.5 GHz bandwidth Maximum PFD frequency of 120 MHz Divide ratios of 8, 16, 32, or 64 2.7 V to 3.3 V power supply Separate charge pump supply (VP) allows extended tuning voltage in 3 V systems RSET contol of charge pump current Hardware power-down mode
GENERAL DESCRIPTION
The ADF4007 is a high frequency divider/PLL synthesizer that can be used in a variety of communications applications. It can operate to 7.5 GHz on the RF side and to 120 MHz at the PFD. It consists of a low noise digital PFD (phase frequency detector), a precision charge pump, and a divider/prescaler. The divider/ prescaler value can be set by two external control pins to one of four values (8, 16, 32, or 64). The reference divider is permanently set to 2, allowing an external REFIN frequency of up to 240 MHz. A complete PLL (phase-locked loop) can be implemented if the synthesizer is used with an external loop filter and a VCO (voltage controlled oscillator). Its very high bandwidth means that frequency doublers can be eliminated in many high frequency systems, simplifying system architecture and reducing cost.
APPLICATIONS
Satellite communications Broadband wireless access CATV Instrumentation Wireless LANs
FUNCTIONAL BLOCK DIAGRAM
VDD VP CPGND RSET
ADF4007
REFIN R COUNTER /2 PHASE FREQUENCY DETECTOR
REFERENCE
CHARGE PUMP
CP
MUX RFINA RFINB N COUNTER / 8, / 16, / 32, / 64
MUXOUT
N2
N1
GND
M2
M1
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
04537-0-001
ADF4007 TABLE OF CONTENTS
Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 4 ESD Caution.................................................................................. 4 Pin Configuration and Function Descriptions............................. 5 Typical Performance Characteristics ............................................. 7 Theory of Operation ........................................................................ 9 Reference Input Section............................................................... 9 RF Input Stage............................................................................... 9 Prescaler P ..................................................................................... 9 R Counter .......................................................................................9 Phase Frequency Detector (PFD) and Charge Pump...............9 MUXOUT ................................................................................... 10 Applications..................................................................................... 11 Fixed High Frequency Local Oscillator................................... 11 Using the ADF4007 as a Divider .............................................. 12 PCB Design Guidelines for Chip Scale Package......................... 13 Outline Dimensions ....................................................................... 14 Ordering Guide .......................................................................... 14
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADF4007 SPECIFICATIONS
AVDD = DVDD = 3 V 10%, AVDD VP 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 k, dBm referred to 50 , TA = TMAX to TMIN, unless otherwise noted. Table 1.
Parameter RF CHARACTERISTICS RF Input Frequency (RFIN) RF Input Frequency REFIN CHARACTERISTICS REFIN Input Sensitivity REFIN Input Frequency REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency3 MUXOUT MUXOUT Frequency3 CHARGE PUMP ICP Sink/Source Absolute Accuracy RSET Range ICP Three-State Leakage Sink and Source Current Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS VIH, Input High Voltage VIL, Input Low Voltage IINH, IINL, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage POWER SUPPLIES AVDD DVDD VP IDD4 (AIDD + DIDD) IP NOISE CHARACTERISTICS Normalized Phase Noise Floor5 B Version1 1.0/7.0 0.5/7.5 Unit GHz min/max GHz min/max Test Conditions/Comments RF input level: +5 dBm to -10 dBm RF input level: +5 dBm to -5 dBm For lower frequencies, ensure that slew rate (SR) > 560 V/s Biased at AVDD/22 For f < 20 MHz, use square wave (slew rate > 50 V/s)
0.8/VDD 20/240 10 100 120 200 5.0 2.5 3.0/11 10 2 1.5 2 1.4 0.6 1 10 VDD - 0.4 0.4 2.7/3.3 AVDD AVDD/5.5 17 2.0 -219
V p-p min/max MHz min/max pF max A max MHz max MHz max mA typ % typ k typ nA max % typ % typ % typ V min V max A max pF max V min V max V min/max V min/max mA max mA max dBc/Hz typ
CL = 15 pF With RSET = 5.1 k With RSET = 5.1 k TA = 85C 0.5 V VCP VP - 0.5 V 0.5 V VCP VP - 0.5 V VCP = VP/2
TA = 25C
IOH = 100 A IOL = 500 A
AVDD VP 5.5 V 15 mA typ TA = 25C
1 2
Operating temperature range (B version) is -40C to +85C. AC coupling ensures AVDD/2 bias. See Figure 13 for typical circuit. 3 Guaranteed by design. Characterized to ensure compliance. 4 TA = 25C; AVDD = DVDD = 3 V; N = 64; RFIN = 7.5 GHz. 5 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PNTOT, and subtracting 20logN (where N is the N divider value) and 10logFPFD. PNSYNTH = PNTOT - 10logFPFD - 20logN. The in-band phase noise (PNTOT) is measured using the HP8562E Spectrum Analyzer from Agilent.
Rev. 0 | Page 3 of 16
ADF4007 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 2.
Parameter AVDD to GND1 AVDD to DVDD VP to GND VP to AVDD Digital I/O Voltage to GND Analog I/O Voltage to GND REFIN, RFINA, RFINB to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature CSP JA Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 s) Infrared (15 s) Transistor Count CMOS Bipolar
1
Rating -0.3 V to +3.6 V -0.3 V to +0.3 V -0.3 V to +5.8 V -0.3 V to +5.8 V -0.3 V to VDD + 0.3 V -0.3 V to VP + 0.3 V -0.3 V to VDD + 0.3 V -40C to +85C -65C to +125C 150C 122C/W 215C 220C 6425 303
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance RF integrated circuit with an ESD rating of <2 kV, and it is ESD sensitive. Proper precautions should be taken for handling and assembly.
GND = AGND = DGND = 0 V.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 4 of 16
ADF4007 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
20 CP 19 RSET 18 VP 17 DVDD 16 DVDD
CPGND 1 AGND 2 AGND 3 RFIN B 4 RFIN A 5
PIN1 INDICATOR
ADF4007
TOPVIEW
15 MUXOUT 14 M1 13 M2 12 N1 11 N2
04537-0-002
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. 1 2, 3 4
5 6, 7
8
9, 10 11, 12 13, 14 15 16, 17
18
19
Mnemonic CPGND AGND RFINB
RFINA AVDD
REFIN
DGND N2, N1 M2, M1 MUXOUT DVDD
VP
RSET
Function Charge Pump Ground. The ground return path of the charge pump. Analog Ground. The ground return path of the prescaler. Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a small bypass capacitor, typically 100 pF. Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO. Analog Power Supply. This pin can range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. AVDD must be the same value as DVDD. Reference Input. A CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of 100 k. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled. Digital Ground. These two bits set the N value. See Table 4. These two bits set the status of MUXOUT and PFD polarity. See Table 5. This multiplexer output allows either the N divider output or the R divider output to be accessed externally. Digital Power Supply. This pin can range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD. Charge Pump Power Supply. This pin should be greater than or equal to VDD. In systems where VDD is 3 V, it can be set to 5 V and used to drive a VCO with a tuning range of up to 5 V. Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The nominal voltage potential at the RSET pin is 0.66 V. The relationship between ICP and RSET is 25.5 I CP MAX = R SET
Therefore, if RSET = 5.1 k, then ICP = 5 mA. Charge Pump Output. When enabled, this pin provides ICP to the external loop filter, which in turn drives the external VCO.
20
CP
Rev. 0 | Page 5 of 16
AVDD 6 AVDD 7 REF IN 8 DGND 9 DGND 10
ADF4007
Table 4. N Truth Table
N2 0 0 1 1 N1 0 1 0 1 N Value 8 16 32 64
Table 5. M Truth Table
M2 0 M1 0 Operation CP: MUXOUT: PFD polarity: CP: MUXOUT: PFD polarity: CP: MUXOUT: PFD polarity: CP: MUXOUT: PFD polarity: Active VDD +ve Three-state R divider output +ve Active N divider output +ve Active GND -ve
0
1
1
0
1
1
Rev. 0 | Page 6 of 16
ADF4007 TYPICAL PERFORMANCE CHARACTERISTICS
Table 6. S-Parameter Data for the RF Input
Frequency1 0.60000 0.70000 0.80000 0.90000 1.00000 1.10000 1.20000 1.30000 1.40000 1.50000 1.60000 1.70000 1.80000 1.90000 2.00000 2.10000 2.20000 2.30000 2.40000 2.50000 2.60000 2.70000 2.80000 2.90000 3.00000 3.10000 3.20000 3.30000 3.40000 3.50000 3.60000 3.70000 3.80000 3.90000 4.00000 4.10000
1
MagS11 0.87693 0.85834 0.85044 0.83494 0.81718 0.80229 0.78917 0.77598 0.75578 0.74437 0.73821 0.72530 0.71365 0.70699 0.70380 0.69284 0.67717 0.67107 0.66556 0.65640 0.63330 0.61406 0.59770 0.56550 0.54280 0.51733 0.49909 0.47309 0.45694 0.44698 0.43589 0.42472 0.41175 0.41055 0.40983 0.40182
AngS11 -19.9279 -23.5610 -26.9578 -30.8201 -34.9499 -39.0436 -42.3623 -46.3220 -50.3484 -54.3545 -57.3785 -60.6950 -63.9152 -66.4365 -68.4453 -70.7986 -73.7038 -75.8206 -77.6851 -80.3101 -82.5082 -85.5623 -87.3513 -89.7605 -93.0239 -95.9754 -99.1291 -102.208 -106.794 -111.659 -117.986 -125.620 -133.291 -140.585 -147.970 -155.978
Frequency1 4.20000 4.30000 4.40000 4.50000 4.60000 4.70000 4.80000 4.90000 5.00000 5.10000 5.20000 5.30000 5.40000 5.50000 5.60000 5.70000 5.80000 5.90000 6.00000 6.10000 6.20000 6.30000 6.40000 6.50000 6.60000 6.70000 6.80000 6.90000 7.00000 7.10000 7.20000 7.30000 7.40000 7.50000
MagS11 0.41036 0.41731 0.43126 0.42959 0.42687 0.43450 0.42275 0.40662 0.39103 0.37761 0.34263 0.30124 0.27073 0.23590 0.17550 0.12739 0.09058 0.06824 0.04465 0.04376 0.06621 0.08498 0.10862 0.12161 0.12917 0.12716 0.11678 0.10533 0.09643 0.08919 0.08774 0.09289 0.10803 0.13956
AngS11 -162.939 -168.232 -174.663 -179.797 174.379 171.537 167.201 163.534 159.829 157.633 152.815 147.632 144.304 138.324 131.087 124.568 119.823 114.960 84.4391 34.2210 4.70571 -12.6228 -26.6069 -38.5860 -47.1990 -55.8515 -63.0234 -66.9967 -75.4961 -89.2055 -103.786 -127.153 -150.582 -170.971
Frequency unit: GHz; parameter type: s; data format: MA; keyword: R; impedance: 50.
Rev. 0 | Page 7 of 16
ADF4007
0 -5 -10 -15 -20 -25 -30 -35 -40 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 RF INPUT FREQUENCY (GHz)
04537-0-003
VDD = 3V VP = 3V
0
REF LEVEL = -14.0dBm
-10 -20
RF INPUT POWER (dBm)
OUTPUT POWER (dB)
-30 -40 -50 -60 -70 -80 -90 -100
-212 -106
VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 106MHz LOOP BANDWIDTH = 1MHz RES BANDWIDTH = 1kHz VIDEO BANDWIDTH = 1kHz SWEEP = 2.5s AVERAGES = 30
TA = +85C
TA = +25C
TA = -40C
-91.0dBc/Hz
04537-0-007
6780 106 FREQUENCY (MHz)
212
Figure 3. Input Sensitivity
0
REF LEVEL = -14.3dBm
Figure 6. Reference Spurs (6.78 GHz RFOUT, 106 MHz PFD, and 1 MHz Loop Bandwidth)
-120 VDD = 3V VP = 5V -130
PHASE NOISE (dBc/Hz)
04537-0-005
-10 -20
OUTPUT POWER (dB)
-30 -40 -50 -60 -70 -80 -90 -100 -2k -1k
VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 106kHz LOOP BANDWIDTH = 1MHz RES BANDWIDTH = 10Hz VIDEO BANDWIDTH = 10Hz SWEEP = 1.9s AVERAGES = 10
-140
-150
-160
-99dBc/Hz
6780M FREQUENCY (Hz)
1k
2k
-180 10k
100k 1M 10M PHASE DETECTOR FREQUENCY (Hz)
120M
Figure 4. Phase Noise (6.78 GHz RFOUT, 106 MHz PFD, and 1 MHz Loop Bandwidth)
-40 -50 -60 10dB/DIV RL = -40dBc/Hz RMS NOISE = 4.2
Figure 7. Phase Noise (Referred to CP Output) vs. PFD Frequency
-6 -5 -4 -3 VP = 5V ICP = 5mA
PHASE NOISE (dBc/Hz)
-70
ICP (mA)
-2 -1 0 1 2
-80 -90 -100 -110
3
-120 -130 -140 10k 100k 1M 10M FREQUENCY OFFSET FROM CARRIER (Hz)
04537-0-006
5 6 0 0.5 1.0 1.5 2.0 2.5 3.0 VCP (V) 3.5 4.0 4.5
100M
5.0
Figure 5. Integrated Phase Noise (6.78 GHz RFOUT, 106 MHz PFD, and 1 MHz Loop Bandwidth)
Figure 8. Charge Pump Output Characteristics
Rev. 0 | Page 8 of 16
04537-0-014
4
04537-0-013
-170
ADF4007 THEORY OF OPERATION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 9. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down.
POWER-DOWN CONTROL
PRESCALER P
The prescaler, operating at CML levels, takes the clock from the RF input stage and divides it down to a manageable frequency for the PFD. The prescaler can be selected to be either 8, 16, 32, or 64, and is effectively the N value in the PLL synthesizer. The terms N and P are used interchangeably in this data sheet. N1 and N2 set the prescaler values. The prescaler value should be chosen so that the prescaler output frequency is always less than or equal to 120 MHz, the maximum specified PFD frequency. Thus, with an RF frequency of 4 GHz, a prescaler value of 64 is valid, but a value of 32 or less is not valid.
f VCO = [N ] x f REFIN 2
NC REFIN
100k
SW2 NC SW1 TO R COUNTER BUFFER
NO
SW3
04537-0-015
R COUNTER
The R counter is permanently set to 2. It allows the input reference frequency to be divided down by 2 to produce the reference clock to the phase frequency detector (PFD).
Figure 9. Reference Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 10 . It is followed by a 2-stage limiting amplifier to generate the CML clock levels needed for the prescaler.
BIAS GENERATOR
500 1.6V
PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP
The PFD takes inputs from the R counter and the N counter (prescaler, P) and produces an output proportional to the phase and frequency difference between them. Figure 11 is a simplified schematic. The PFD includes a fixed, 3 ns delay element that controls the width of the antibacklash pulse. This pulse ensures that there is no dead zone in the PFD transfer function and minimizes phase noise and reference spurs.
VP CHARGE PUMP
AVDD
500
RFINA
RFINB
LOGIC HI
04537-0-016
D1
Q1 U1
UP
R DIVIDER
CLR1
AGND
Figure 10. RF Input Stage
3ns DELAY
U3 CP
LOGIC HI
CLR2 DOWN D2 Q2 U2
04537-0-017
N DIVIDER CPGND
Figure 11. PFD Simplified Schematic and Timing (In Lock)
Rev. 0 | Page 9 of 16
ADF4007
MUXOUT
The output multiplexer on the ADF4007 allows the user to access various internal points on the chip. The state of MUXOUT is controlled by the M2 and M1 pins. Figure 12 shows the MUXOUT section in block diagram form.
DVDD
PFD Polarity
The PFD polarity is set by the state of M2 and M1 pins as given in the Table 5. The ability to set the polarity allows the use of VCOs with either positive or negative tuning characteristics. For standard VCOs with positive characteristics (output frequency increases with increasing tuning voltage), the polarity should be set to positive. This is accomplished by tying M2 and M1 to a logic low state.
DVDD
CP Output
MUX CONTROL MUXOUT
R COUNTER OUTPUT N COUNTER OUTPUT DGND
DGND
Figure 12. MUXOUT Circuit
Rev. 0 | Page 10 of 16
04537-0-018
The CP output state is also controlled by the state of M2 and M1. It can be set either to active (so that the loop can be locked) or to three-state (open the loop). The normal state is CP output active.
ADF4007 APPLICATIONS
FIXED HIGH FREQUENCY LOCAL OSCILLATOR
Figure 13 shows the ADF4007 being used with the HMC358MS8G VCO from Hittite Microwave Corporation to produce a fixed-frequency LO (local oscillator), which could be used in satellite or CATV applications. In this case, the desired LO is 6.7 GHz. The reference input signal is applied to the circuit at FREFIN and, in this case, is terminated in 50 . Many systems would have either a TCXO or an OCXO driving the reference input without any 50 termination. To bias the REFIN pin at AVDD/2, ac coupling is used. The value of the coupling capacitor used depends on the input frequency. The equivalent impedance at the input frequency should be less than 10 . Given that the dc input impedance at the REFIN pin is 100 k, less than 0.1% of the signal is lost. The charge pump output of the ADF4007 drives the loop filter. In calculating the loop filter component values, a number of items need to be considered. In this example, the loop filter was designed so that the overall phase margin for the system is 45. Other PLL system specifications are as follows: KD = 5 mA KV = 100 MHz/V Loop Bandwidth = 300 kHz FPFD = 106 MHz N = 64 All these specifications are needed and used with the ADIsimPLL to derive the loop filter component values shown in Figure 13. The circuit in Figure 13 gives a typical phase noise performance of -100 dBc/Hz at 10 kHz offset from the carrier. Spurs are heavily attenuated by the loop filter and are below -90 dBc. The loop filter output drives the VCO, which, in turn, is fed back to the RF input of the PLL synthesizer and also drives the RF output terminal. A T-circuit configuration provides 50 matching between the VCO output, the RF output, and the RFIN terminal of the synthesizer.
AVDD = 3.3V
VCC = 3.3V
18k
6 7 16 17 18
1k
VCC = 12V 1k
18
AVDD AVDD DVDD DVDD
5 4
VP CP 20 5.6nF 22 47nF
RFINA RFINB
HMC358MS8G
10pF VCO 100MHz/V
100pF 18
18 100pF RFOUT
AD820
ADF4007
100pF FREFIN 51 LOGIC HI LOGIC HI LOGIC LO LOGIC LO 100pF
8 11 12 13 14 19
REFIN N2 N1 M2 M1 RSET GND 10 MUXOUT 15
GND
GND
GND
RSET 5.1k
100pF
2
3
9
NOTE DECOUPLING CAPACITORS (0.1mF/10pF) ON AV , DVDD, AND VP OF THE ADF4007 AND ON DD VCC OF THE AD820 AND THE HMC358MS8G HAVE BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.
Figure 13. 6.78 GHz Local Oscillator Using the ADF4007
Rev. 0 | Page 11 of 16
04537-0-019
ADF4007
USING THE ADF4007 AS A DIVIDER
In addition to its use as a standard PLL synthesizer, the ADF4007 can also be used as a high frequency counter/divider with a value of 8, 16, 32, or 64.This can prove useful in a wide variety of applications where a higher frequency signal is readily available. Figure 14 shows the ADF4007 used in this manner with the ADF4360-7.
VVCO VDD LOCK DETECT 4.7k 10F
14 CN 6 21 2 23 20
This part is an integrated synthesizer and VCO, in this case operating over a range of 1200 MHz to 1500 MHz. With divideby-8 chosen in the ADF4007 (N2 = 0, N1 = 0), the output range is 150 MHz to 187.50 MHz.
VDD
RSET 13k CP 24 6.8nF 470pF 6.2k 220pF
CP
VP
AVDD DVDD
M2
M1
VVCO DVDD AVDD 1nF 1nF FREFIN
16 REF IN
CE
MUXOUT VTUNE 7 CHARGE PUMP PHASE FREQUENCY DETECTOR MUXOUT MUX CMOS OUTPUT
51
17 CLK 18 DATA 19 LE
ADF4360-7
VVCO 51 RFOUTA 4 51 100pF RFINB 100pF CPGND GND N1 N2 REFIN R COUNTER /2 RFINA N COUNTER /8, /16 /32, /64
SPI COMPATIBLE SERIAL BUS
12 C C
1nF 4.7k
13 RSET
CPGND
1 3
AGND
8 11
DGND
22 15
L1
9
L2
10
RFOUTB 5
ADF4007
2.2nH
2.2nH
Figure 14. Using the ADF4007 to Divide-Down the Output of the ADF4360-7
Rev. 0 | Page 12 of 16
04537-0-020
ADF4007 PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE
The lands on the chip scale package (CP-20) are rectangular. The printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. The land should be centered on the pad to ensure that the solder joint size is maximized. The bottom of the chip scale package has a central thermal pad. The thermal pad on the printed circuit board should be at least as large as this exposed pad. The printed circuit board should have a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern to ensure that shorting is avoided. Thermal vias may be used on the printed circuit board thermal pad to improve thermal performance of the package. If vias are used, they should be incorporated in the thermal pad at 1.2 mm pitch grid. The via diameter should be between 0.30 mm and 0.33 mm, and the via barrel should be plated with 1 oz. copper to plug the via. The user should connect the printed circuit board thermal pad to AGND.
Rev. 0 | Page 13 of 16
ADF4007 OUTLINE DIMENSIONS
4.0 BSC SQ 0.60 MAX PIN 1 INDICATOR TOP VIEW 3.75 BSC SQ 0.75 0.55 0.35 12 MAX 1.00 0.85 0.80 SEATING PLANE 0.50 BSC 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.20 REF COPLANARITY 0.08
11 10
0.60 MAX
16 15 20 1
BOTTOM VIEW
6 5
2.25 2.10 SQ 1.95
0.25 MIN 0.30 0.23 0.18
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1
Figure 15. 20-Lead Frame Chip Scale Package [LFCSP] (CP-20) Dimensions shown in millimeters
ORDERING GUIDE
Model ADF4007BCP ADF4007BCP-REEL ADF4007BCP-REEL7
CP = chip scale package.
Temperature Range -40C to + 85C -40C to + 85C -40C to + 85C
Package Description 20-lead frame chip scale package (LFCSP) 20-lead frame chip scale package (LFCSP) 20-lead frame chip scale package (LFCSP)
Package Option CP-20 CP-20 CP-20
Rev. 0 | Page 14 of 16
ADF4007 NOTES
Rev. 0 | Page 15 of 16
ADF4007 NOTES
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04537-0-2/04(0)
Rev. 0 | Page 16 of 16
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